1. Field of the Invention
The present invention relates to a delta-sigma modulated fractional-N PLL frequency synthesizer and a wireless communication apparatus having the same frequency synthesizer.
2. Description of Related Art
In the past, a delta-sigma modulator is constructed to integrate input signals and quantizes them using one or more bits. For example, the delta-sigma modulator is applied to A/D (analog/digital) converters, D/A (digital/analog) converters, PLL (Phase Locked Loop) circuits, and the like.
With respect to a transfer function of the delta-sigma modulator to a quantization noise, the transfer function is characterized to be small in a low frequency region and large in a high frequency region. That is, the delta-sigma modulator allows quantization noise components in an output signal to concentrate in the high frequency region. Accordingly, the delta-sigma modulator supplies output signals with noise components suppressed in a given band. Such effect of suppressing noise components is generally called “noise shaping”.
In wireless communication apparatuses such as cellular phones, a frequency synthesizer including a PLL circuit is generally used as a local oscillator of a frequency converter (mixer).
An integer-N PLL circuit, which is an example of PLL circuits, receives a signal obtained by dividing a reference frequency signal from the reference oscillator and a signal obtained by dividing a frequency signal from a voltage controlled oscillator (VCO) at a phase comparator to implement phase-locked operation. Therefore, the oscillated frequency of VCO is an integral multiple of a comparison frequency input to the phase comparator. This means that the comparison frequency needs to be lowered as the wireless communication system requires smaller channel steps. On the other hand, decreasing the comparison frequency increases the time (lockup time) needed for channel switching. There is trade-off relationship between the comparison frequency and the lockup time.
The fractional-N PLL is known as a technology to solve this trade-off and enables operations at a channel step smaller than the comparison frequency. As one of techniques to realize the fractional-N PLL, there is known a technology using the delta-sigma modulator (i.e., a delta-sigma modulated fractional-N PLL frequency synthesizer).
FIG. 6 shows the schematic construction of a related delta-sigma modulated fractional-N PLL frequency synthesizer.
In FIG. 6, a terminal 101 is supplied with a signal having a phase comparison frequency fcomp that is generated by dividing a reference frequency signal from a reference oscillator (not shown). The phase comparison frequency fcomp signal is input to a phase comparator 102. The phase comparator 102 detects a phase difference between the phase comparison frequency fcomp signal supplied from the terminal 101 and a frequency signal generated from a divider 108 by dividing by N an output frequency from a subsequent voltage controlled oscillator (VCO) 105. The phase comparator 102 outputs a phase difference signal that represents the phase difference in binary. The phase difference signal output from the phase comparator 102 is supplied to a charge pump 103.
The charge pump 103 converts the binary phase difference signal from the phase comparator 102 into ternary. The charge pump 103 supplies or is supplied with currents corresponding to the three values to generate current signals proportional to the above-mentioned phase difference. An output current signal from the charge pump 103 is supplied to a low pass filter (LPF) 104.
The low pass filter 104 smoothes the output current signal from the charge pump 103 and converts it into a voltage signal. An output voltage signal from the low pass filter 104 is used for controlling a voltage controlled oscillator 105.
The voltage controlled oscillator 105 outputs a signal having oscillation frequency fvco in accordance with the output voltage signal from the low pass filter 104. The oscillation frequency fvco signal is provided to subsequent circuitry (such as a frequency converter) as an output signal from the delta-sigma modulated fractional-N PLL frequency synthesizer via a terminal 106. Further, the oscillation frequency fvco signal is divided by the divider 108 and is fed back to the phase comparator 102.
A register 111 stores data representing integral parts and fractional parts of the divided data. The register 111 supplies an adder 109 with integral part data including a plurality of bits to represent the integral part. The register 111 supplies a delta-sigma modulator 113 with fractional part data F including a plurality of bit store present the fractional part.
The delta-sigma modulator 113 integrates the supplied fractional part data F, quantizes it, and then outputs it to the adder 109.
The adder 109 adds the integral part data to output data from the delta-sigma modulator 113. The added data is supplied to the divider 108.
Thus, the divider 108 divides outputs from the voltage controlled oscillator 105 in accordance with an output signal from the delta-sigma modulator 113 to implement fractional-N.
For example, when the delta-sigma modulator 113 uses the number of bits M and the phase comparison frequency corresponds to fcomp as mentioned above, channel steps equal fcomp×(F/(2 to the Mth power)).
The delta-sigma modulator may be supplied with an input signal representing a specific value (e.g., an exponential in binary). In this case, as shown in FIG. 7, there occurs a problem of generating a quantization noise as a spurious tone. In FIG. 7, the abscissa represents frequencies and the ordinate represents quantization noises.
Since the spurious tone occurs within a PLL's loop band, a loop filter, if used, cannot suppress the spurious tone. As a result, the wireless communication apparatus performance may be greatly affected.
In the past, spurious tones are prevented from occurring by increasing the number of bits for the delta-sigma modulator and, instead of suspected fractional part data F, using adjacent data (F−1 or F+1).
However, increasing the number of bits for the delta-sigma modulator enlarges the circuit scale. The output frequency slightly deviates from an intended frequency.
Japanese Published Unexamined Patent Application No. 3461799 (patent document 1) proposes the technology to be able to avoid a spurious tone in suspected fractional part data F. That is, there is provided the digital dither circuit that alternately selects two values F−k and F+k (where k is an integer) at a cycle half the comparison frequency.
FIG. 8 shows the schematic construction of a delta-sigma modulated fractional-N PLL frequency synthesizer having the digital dither circuit. The mutually corresponding parts in FIGS. 8 and 6 are designated by the same reference numerals and a detailed description is omitted for simplicity.
In FIG. 8, a digital dither circuit 112 is supplied with the above-mentioned fractional part data F from a register 111. The digital dither circuit 112 alternately selects two values F−k and F+k at a cycle half the comparison frequency and outputs the selected value to the delta-sigma modulator 13.
[Patent document 1] Japanese Published Unexamined Patent Application No. 3461799 (FIG. 1)
However, providing the digital dither circuit 112 as shown in FIG. 8 is unpreferable because the circuit scale is enlarged. Further, the digital dither circuit 112 is constructed to alternately output two values F−k and F+k that are used instead of suspected fractional part data F. When F+k is data to generate a spurious tone, for example, an operation is assumed to be problematic.